ARM ARM966E-S Technical Reference Manual page 7

List of Tables
ARM966E-S Technical Reference Manual
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Table 4-1
Table 5-1
Table 5-2
Table 5-3
Table 7-1
Table 8-1
Table 8-2
Table 8-3
Table 10-1
Table 10-2
Table 11-1
Table 11-2
Table 11-3
Table 11-4
ARM DDI 0186A
Change history .............................................................................................................. ii
CP15 register map .................................................................................................... 2-4
Register 0, ID code ................................................................................................... 2-5
Register 1, Control register ....................................................................................... 2-5
Register 13, Trace process identifier ........................................................................ 2-9
Register 15, Test register map .................................................................................. 2-9
Trace control register .............................................................................................. 2-10
BIST control register ............................................................................................... 2-10
BIST size encoding examples ................................................................................. 2-11
I-SRAM stall cycles ................................................................................................... 4-3
Simultaneous access behavior ................................................................................. 5-3
DMAENABLE setup and hold cycles with respect to DMAnREQ ............................ 5-11
DMA signal behavior ............................................................................................... 5-12
Handshake encoding ................................................................................................ 7-6
Scan chain 15 addressing mode bit order ................................................................. 8-7
Mapping of scan chain 15 address field to CP15 registers ....................................... 8-7
Coprocessor 14 register map .................................................................................. 8-19
Instruction BIST address and general registers ...................................................... 10-5
Data BIST address and general registers ............................................................... 10-6
I-SRAM access ....................................................................................................... 11-4
D-SRAM access ...................................................................................................... 11-5
Key to tables ........................................................................................................... 11-7
AHB read and unbuffered write transfer cycles ....................................................... 11-7
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