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Coprocessor Interface
7.3
MCR/MRC
Coprocessor
pipeline
CLK
CPINSTR[31:0]
nCPMREQ
CPPASS
CPLATECANCEL
CHSDE[1:0]
CHSEX[1:0]
CPDIN[31:0]
MRC
CPDOUT[31:0]
MCR
7-8
These cycles look very similar to
in Figure 7-2. First nCPMREQ is driven LOW to denote that the instruction on
CPINSTR[31:0] is entering the Decode stage of the pipeline. This causes the
coprocessor to decode the new instruction and drive CHSDE[1:0]. In the next cycle
nCPMREQ is driven LOW to denote that the instruction has now been issued to the
Execute stage. If the condition codes passes, and the instruction is to be executed, the
CPPASS signal is driven HIGH and the CHSDE[1:0] handshake bus is examined (it is
ignored in all other cases).
Fetch
MCR/MRC
For any successive Execute cycles the CHSEX[1:0] handshake bus is examined. When
the LAST condition is observed, the instruction is committed. In the case of a
CPDOUT[31:0] bus is driven with the registered data. In the case of a
CPDIN[31:0] is sampled at the end of the ARM9E-S core Memory stage and written
to the destination register during the next cycle.
Copyright © 2000 ARM Limited. All rights reserved.
/
. An example, with a busy-wait state, is shown
STC
LDC
Decode
Execute
Execute
(WAIT)
(LAST)
WAIT
LAST
Ignored
Figure 7-2 MCR/MRC transfer timing with busy-wait
Memory
Write
Coproc to ARM
ARM to coproc
MCR
,
MRC
ARM DDI 0186A
, the
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