Table of Contents
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Index
nIRQ A-11
RTCK 8-3
SCANEN A-14
SERIALEN A-14
SI A-14
SO A-14
SYSCLKEN 8-14
TAPID A-10
TCK 8-3
TESTEN A-14
VINITHI A-11
SO A-14
SRAM
address space 3-3
enable 2-6
requirements 4-2
synchronous 4-2
SRAM stall cycles 4-3
SRAM wrapper 4-7
Standby mode 2-8
States, TAP controller 8-2
State, debug 8-2
SYSCLKEN 8-14
System state, determining 8-15
T
TAP controller 8-5, 8-16
states 8-2
TAPID A-10
TBIT 2-6
TCK 8-3
Test
clock 8-3
register 2-9
Test Access Port 8-2
TESTEN A-14
Thumb instruction set 1-2
Typographical conventions xiii
V
VINITHI A-11
Index-4
W
Wait for interrupt 2-8
Watchpoints 8-11, 8-16, 8-17
exceptions 8-12
timing 8-11
Write address space 3-4
Write buffer enable 2-7
Copyright © 2000 ARM Limited. All rights reserved.
ARM DDI 0186A
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