Figure 6-9 Single Ldm Followed By Sequential Instruction Fetch; Stm Crossing A 1Kb Boundary - ARM ARM966E-S Technical Reference Manual

Bus Interface Unit
CLK
HTRANS
HADDR
HWRITE
HWDATA
HREADY
6-14
NONSEQ
DA-1

Figure 6-9 Single LDM followed by sequential instruction fetch

Note
The NONSEQ cycle of the instruction fetch replaces the second IDLE cycle that occurs
when an AHB data access is required following the

STM crossing a 1KB boundary

AMBA Rev.2 Specification states that sequential accesses must not cross 1KB
boundaries. The ARM966E-S splits sequential accesses that cross a 1KB boundary into
two sets of separate accesses.
Figure 6-10 on page 6-15 shows bus activity when a
1KB boundary. DA-3 is the first address in a new 1KB region. The two sets of transfers
each begin with a nonsequential access type, and are separated by an IDLE cycle.
Copyright © 2000 ARM Limited. All rights reserved.
SEQ SEQ IDLE
DA-2 DA-3
DD-1 DD-2
NONSEQ IDLE
IA-1
DD-3
.
LDM
writing four words, crosses a
STM
ARM DDI 0186A
SEQ
IA-3
ID-1