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Test Support
10.3
BIST of tightly-coupled SRAM
10.3.1
BIST control register
10-4
Adding a simple memory test controller allows an exhaustive test of the memory arrays
to be performed. BIST test is activated by an
can be run on one or both of the I-SRAM and D-SRAM simultaneously.
When a BIST test is performed on an SRAM, the functional enable for that SRAM is
automatically disabled, forcing all memory accesses to that SRAM address space to go
to the AHB. This enables BIST tests to be run in the background. For instance, the
instruction SRAM can be BIST tested, while code is executed over the AHB.
Full programmer control over the BIST mechanism is achieved through five registers
that are mapped to CP15 register 15 address space. For details of the
instructions used to access these registers, see Register 15, Test on page 2-9. Access to
these registers is also available in debug mode, see ARM966E-S scan chain 15 on
page 8-7.
This controls the operation of the SRAM memory BIST. Before initiating a BIST test,
a
is first performed to the BIST control register to set up the size of the test and
MCR
enable the SRAM to be tested. A further
The current status of a BIST test and result of a completed test can be accessed by
performing an
to the BIST control register. This returns flags to indicate that a test
MRC
is:
•
running
•
paused
•
failed
•
completed.
In addition to returning the state for the size of the test and SRAM enable status, having
completed a BIST test, the BIST enable must first be cleared by writing to the BIST
control register if the SRAM is to be used by you for functional operation. The SRAM
must then be re-enabled by writing to CP15 register 1. This is necessary as the BIST test
enable automatically clears the functional enable.
Copyright © 2000 ARM Limited. All rights reserved.
to the CP15 BIST control register and
MCR
is required to initiate the test.
MCR
or
MCR
MRC
ARM DDI 0186A
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