Miscellaneous Signals; A.6 Miscellaneous Signals - ARM ARM966E-S Technical Reference Manual

A.6

Miscellaneous signals

ARM DDI 0186A
Table A-5 describes the ARM966E-S miscellaneous signals.
Name Direction
nFIQ Input
Not fast interrupt
request
nIRQ Input
Not interrupt request
VINITHI Input
Exception vector
location at reset
INITRAM Input
Tightly-coupled
SRAM enable at
reset
BIGENDOUT Output
Copyright © 2000 ARM Limited. All rights reserved.
Table A-5 Miscellaneous signals
Description
This is the Fast Interrupt Request signal. This signal
must be synchronous to CLK.
This is the Interrupt Request signal. This signal must
be synchronous to CLK.
Determines the reset location of the exception
vectors. When LOW, the vectors are located at
. When HIGH, the vectors are located at
0x00000000
.
0xFFFF0000
Determines the tightly-coupled SRAM reset
enable.When HIGH, the instruction and data SRAM
are both enabled during reset, when LOW, the SRAM
are disabled during reset.
When HIGH, the ARM966E-S treats bytes in
memory as being in big-endian format. When LOW,
memory is treated as little-endian.
Signal Descriptions
A-11