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7.2.1
Coprocessor handshake states
ARM DDI 0186A
•
the instruction in the Decode stage of the coprocessor pipeline must enter its
Execute stage
•
the fetched instruction must be sampled.
In all other cases, the ARM9E-S pipeline is stalled, and the coprocessor pipeline must
not advance.
During the Execute stage, the condition codes are compared with the flags to determine
whether the instruction really executes or not. The output CPPASS is asserted, HIGH,
if the instruction in the Execute stage of the coprocessor pipeline:
•
is a coprocessor instruction
•
has passed its condition codes.
If a coprocessor instruction busy-waits, CPPASS is asserted on every cycle until the
coprocessor instruction is executed. If an interrupt occurs during busy-waiting,
CPPASS is driven LOW, and the coprocessor stops execution of the coprocessor
instruction.
Another output, CPLATECANCEL, cancels a coprocessor instruction when the
instruction preceding it caused a data abort. This is valid on the rising edge of CLK on
the cycle that follows the first Execute cycle of the coprocessor instructions. This is the
only cycle in which CPLATECANCEL can be asserted.
On the rising edge of the clock, the ARM9E-S processor examines the coprocessor
handshake signals CHSDE[1:0] or CHSEX[1:0]:
•
If a new instruction is entering the Execute stage in the next cycle, it examines
CHSDE[1:0].
•
If the currently executing coprocessor instruction requires another Execute cycle,
it examines CHSEX[1:0].
The handshake signals encode one of four states:
ABSENT
If there is no coprocessor attached that can execute the coprocessor
instruction, the handshake signals indicate the ABSENT state. In this
case, the ARM9E-S takes the undefined instruction trap.
WAIT
If there is a coprocessor attached that can handle the instruction, but not
immediately, the coprocessor handshake signals are driven to indicate
that the ARM9E-S processor core must stall until the coprocessor can
catch up. This is known as the busy-wait condition. In this case, the
ARM9E-S processor core loops in an IDLE state waiting for
Copyright © 2000 ARM Limited. All rights reserved.
Coprocessor Interface
7-5
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