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ARM DDI 0186A
Natural write buffer drain
When a write is being committed to the write buffer FIFO, a signal is sent to the BIU to
initiate an AHB write. The BIU then pops the address for the write from the FIFO
followed by the data and starts an AHB transfer (assuming the ARM966E-S is the
granted bus master). This process might take several cycles because the slave being
accessed for the write might have a multi-wait cycle response. Additionally, the AHB
can be run at a lower rate than the ARM966E-S system introducing extra delay to the
buffered write process. This can lead to the core trying to commit data at a higher rate
than the FIFO can be drained, resulting in the FIFO becoming full. The ARM9E-S core
is stalled until an entry becomes available.
When an address is placed in the write buffer, a marker is also stored to indicate if the
size of the write is, byte, halfword or word. If a
is stored with the data, to indicate to the BIU that the address incrementer must be used
to produce the AHB address for the second and following writes of the
mechanism allows only one FIFO entry to be used for the address, leaving more room
for data (see Figure 6-1 on page 6-4).
If a
crosses a 1KB boundary, the AHB specification requires that the first access in
STM
the new 1KB region is a nonsequential access. This allows the BIU to have a small 1KB
incrementer, because the ARM9E-S data address can be resampled during the
nonsequential cycle. For this reason, the write buffer must also break up accesses that
cross a 1KB region, by forcing the sequentiality marker LOW for the preceding data
location and committing an extra address entry at the start of the new region.
Note
Because the ARM9E-S core is free to continue program execution following a buffered
write, without having to wait for the write to complete on the AHB, external Data
Aborts can not be returned by buffered writes.
Enforced write buffer drain
There are two situations where the core is stalled and the write buffer is forced to drain
completely before program execution can continue:
•
an instruction fetch, data load, or unbuffered write to the AHB is being requested
•
a drain write buffer instruction is being executed.
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is performed, a sequentiality marker
STM
Bus Interface Unit
. This
STM
6-5
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