Figure 5-5 Dual-Port Dma Reads - ARM ARM966E-S Technical Reference Manual

Direct Memory Access (DMA)
CLK
DMAENABLE
DMAnREQ
DMAWait
DMAnRW
DMAReady
DMAAddr
DMARData
5.2.4 Dual-port RAM writes
5-8
DMAENABLE must be asserted one cycle prior to a request being made and can be
deasserted one cycle prior to the last read data being returned
.
Figure 5-6 on page 5-9 shows dual-port write operations to a dual-port RAM.
A write request is initiated by taking DMAnREQ LOW and DMAnRW HIGH. The
address, DMAAddr, and write data, DMAWData, must be valid in the same cycle. The
write to the RAM happens in the following cycle, due to the one cycle latency of the
input registers.
Note
Because the ARM966E-S core does not need to be stalled for dual-port DMA accesses,
the DMA controller can access the data RAM continuously. DMAWait must be tied
LOW otherwise the DMA access is by the first port of the RAM and the interface
behaves as described in Single-port RAM writes on page 5-6.
Copyright © 2000 ARM Limited. All rights reserved.
Read1 Read2
A1 A2
D1 D2

Figure 5-5 Dual-port DMA reads

ARM DDI 0186A