ARM ARM966E-S Technical Reference Manual page 4

Contents
Chapter 5
Chapter 6
Chapter 7
Chapter 8
Chapter 9
Chapter 10
iv
4.3 Enabling the SRAM .................................................................................... 4-4
4.4 ARM966E-S SRAM wrapper ...................................................................... 4-7
Direct Memory Access (DMA)
5.1 About the DMA interface ............................................................................ 5-2
5.2 Timing interface .......................................................................................... 5-5
5.3 DMAENABLE setup and hold cycles ........................................................ 5-11
5.4 Summary of signal behavior ..................................................................... 5-12
Bus Interface Unit
6.1 About the BIU and write buffer ................................................................... 6-2
6.2 Write buffer operation ................................................................................. 6-3
6.3 AHB bus master interface ........................................................................... 6-7
6.4 AHB clocking ............................................................................................ 6-17
Coprocessor Interface
7.1 About the coprocessor interface ................................................................. 7-2
7.2 LDC/STC .................................................................................................... 7-4
7.3 MCR/MRC .................................................................................................. 7-8
7.4 Interlocked MCR ......................................................................................... 7-9
7.5 CDP .......................................................................................................... 7-10
7.6 Privileged instructions ............................................................................... 7-11
7.7 Busy-waiting and interrupts ...................................................................... 7-12
Debug Support
8.1 About the debug interface .......................................................................... 8-2
8.2 Debug systems ........................................................................................... 8-4
8.3 ARM966E-S scan chain 15 ........................................................................ 8-7
8.4 Debug interface signals .............................................................................. 8-9
8.5 ARM9E-S core clock domains .................................................................. 8-14
8.6 Determining the core and system state .................................................... 8-15
8.7 About the EmbeddedICE-RT .................................................................... 8-16
8.8 Disabling EmbeddedICE-RT .................................................................... 8-18
8.9 The debug communications channel ........................................................ 8-19
8.10 Monitor mode debug ................................................................................. 8-23
8.11 Debug additional reading .......................................................................... 8-25
Embedded Trace Macrocell Interface
9.1 About the ETM interface ............................................................................. 9-2
9.2 Enabling the ETM interface ........................................................................ 9-3
9.3 ARM966E-S trace support features ............................................................ 9-4
Test Support
10.1 About the ARM966E-S test methodology ................................................. 10-2
10.2 Scan insertion and ATPG ......................................................................... 10-3
10.3 BIST of tightly-coupled SRAM .................................................................. 10-4
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