Figure 8-4 Breakpoint Timing - ARM ARM966E-S Technical Reference Manual

Debug Support
CLK
IA[31:1]
INSTR[31:0]
DBGIEBKPT
DBGACK
8.4.2 Breakpoints and exceptions
8-10
F1 D1
F2
1 2
A breakpointed instruction can have a Prefetch Abort associated with it. If so, the
Prefetch Abort takes priority and the breakpoint is ignored. (If there is a prefetch abort,
instruction data might have been invalid, the breakpoint might have been
data-dependent, and as the data might be incorrect, the breakpoint might have been
triggered incorrectly.)
SWI and undefined instructions are treated in the same way as any other instruction that
might have a breakpoint set on it. Therefore, the breakpoint takes priority over the
or undefined instruction.
On an instruction boundary, if there is a breakpointed instruction and an interrupt
(nIRQ or nFIQ), the interrupt is taken and the breakpointed instruction is discarded.
When the interrupt is being serviced, the execution flow is returned to the original
program. This means that the instruction that was previously breakpointed is fetched
again, and if the breakpoint is still set, the processor enters debug state when it reaches
the Execute stage of the pipeline.
When the processor enters halt mode debug state, it is important that further interrupts
do not affect the instructions executed. For this reason, as soon as the processor enters
stop-mode debug state, interrupts are disabled, although the state of the I and F bits in
the Program Status Register (PSR) are not affected.
Copyright © 2000 ARM Limited. All rights reserved.
Ddebug
E1 M1 W1
D2 E2 M2
F1 D1 E1
3
Edebug1 Edebug2
W2
M1 W1
4

Figure 8-4 Breakpoint timing

ARM DDI 0186A
SWI