Table 11-7 Interrupt Latency Calculated Examples - ARM ARM966E-S Technical Reference Manual

ARM DDI 0186A
The (r0-pc) must complete before the interrupt vector is fetched. The write buffer
LDM
drain must be added to this, in addition to assuming that the LDM (r0-pc) crosses a 1KB
boundary.
The calculation assumes that once the interrupt has entered the Decode stage of the
ARM9E-S pipeline following the instruction fetch to (pc+1), the subsequent fetches to
the interrupt vector are serviced by the tightly-coupled SRAM, requiring a further three
CLK cycles for the FIQ handler to enter execute. (This is not the case if the interrupt
vector resides at the HIVECS location of
The cycles from Table 11-6 on page 11-10 are added to the three CLK cycles from the
tightly-coupled SRAM to produce the interrupt latency equation:
Interrupt latency CLK = 2Sync+9N+14S+2B+11I+3
Rewriting in terms of R, NONSEQ, SEQ and IDLE the equation simplifies to:
Interrupt latency CLK =R (9 NONSEQ+14SEQ+13)+1
where IDLE=BUSY=R as this is a single HCLK cycle by definition.
The number of CLK cycles latency can now be derived for different AHB clocking
ratios and for the differing AHB slave responses that might exist in the AHB system to
which the ARM966E-S interfaces. Table 11-7 gives examples of interrupt latency for
systems with different CLK to HCLK ratios. For each system, slaves can have different
response times to NONSEQ and SEQ transfers. Table 11-7 gives some examples of
different slave responses and the resultant interrupt latency in CLK cycles.
Latency when
CLK to HCLK
NONSEQ = 1,
Ratio - R
SEQ = 1
1 37
2 73
3 109
4 145
Copyright © 2000 ARM Limited. All rights reserved.
0xFFFF 0000 . This requires AHB access.)

Table 11-7 Interrupt latency calculated examples

Latency when
NONSEQ= 2,
SEQ = 1
46
91
136
181
Instruction cycle timings
Latency when
NONSEQ = 2,
SEQ = 2
60
119
178
237
11-11