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Debug Support
Bit [38]
Bits[37:32]
1
1 1111 0
0
1 1111 1
1
1 1111 1
8-8
Table 8-2 Mapping of scan chain 15 address field to CP15 registers (continued)
Bits[31:30]
11
11
11
The scan address decode overloads the existing functional decode logic that is used to
access the CP15 registers during
registers on page 2-4.
The decode overload is performed as follows:
Bit [37]
Corresponds to Opcode 1 of an
Bit [36:33]
Correspond to the CRn field of an
Bit [32]
Corresponds to bit 0 of the Opcode 2 field of an
Bits [2:1]
Of opcode 2 are tied to 00 during debug state.
The debug scan chain, SC15, only allows access to bit[0] of the OpCode2 field by
default. To allow access to the Address and General BIST registers within CP15
Register 15, bits [31:30] of SC15 are overloaded as shown in Table 8-2 on page 8-7.
There are certain restrictions with the overloading; when writing to the BIST General
registers (i.e. writing a new seed), bits[31:30] of the seed are restricted to those values
shown in Table 8-2 on page 8-7. These bits are not used in the BIST Address registers
and so there are no debug restrictions when accessing these registers.
The ability to control the ARM966E-S system state through scan chain 15 provides
extra debug visibility. For example, if the debugger wishes to compare the contents of
an address that maps to the I-SRAM or D-SRAM, with the same address in external
memory, the debugger can:
1.
Load from the address with the SRAM enabled to return the SRAM data.
2.
Disable the SRAM.
3.
Perform the load again. The second load now accesses the AHB because the
SRAM is disabled, returning the value from AHB memory.
Copyright © 2000 ARM Limited. All rights reserved.
CP15 reg number
C15
C15
C15
and
instructions (see ARM966E-S CP15
MCR
MRC
MCR
MCR
Meaning
Write DBIST address
Read DBIST general
Write DBIST general
or
instruction.
MRC
or
instruction.
MRC
MCR or MRC
ARM DDI 0186A
instruction.
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