I-Sram Write Followed By Instruction Fetch, Data Read - ARM ARM966E-S Technical Reference Manual

SRAM Stall Cycles
I-SRAM I-SRAM SRAM read
write cycle write cycle cycle
stall stall
cycle cycle
CLK
DnMREQ
DnRW
Addr A (write) Addr B (write)
DA[31:1]
Addr C (Ifetch)
IA[31:1]
InMREQ
Addr A Addr B Addr C
I-SRAM Addr
Write data (A) Write data (B)
WDATA[31:0]
Read instr (C)
INSTR[31:0]
SYSCLKEN
Figure C-8 I-SRAM write followed by instruction fetch, data write

I-SRAM write followed by instruction fetch, data read

This is where a write is taking place to the I-SRAM that is immediately followed by
both an instruction fetch and a data read. This has the same two-stall cycle response as
the previous scenario, although the I-SRAM control behaves differently. The first write
must complete before the data read can be performed. The instruction fetch can then be
performed in the next cycle (see Figure C-9 on page C-10).
ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. C-9