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ARM DDI 0186A
Name
Direction
COMMTX
Output
Communications
channel transmit
DBGACK
Output
Debug acknowledge
DBGEN
Input
Debug enable
DBGRQI
Output
Internal debug
request
EDBGRQ
Input
External debug
request
DBGEXT[1:0]
Input
EmbeddedICE
external input
DBGINSTREXEC
Output
Instruction executed
DBGRNG[1:0]
Output
EmbeddedICE
Rangeout
Copyright © 2000 ARM Limited. All rights reserved.
Table A-4 Debug signals (continued)
Description
When HIGH, denotes that the comms channel
transmit buffer is empty.
When HIGH indicates that the processor is in debug
state.
Enables the debug features of the processor. This
signal must be tied LOW if debug is not required.
Represents the debug request signal that is presented
to the core debug logic. This is a combination of
EDBGRQ and bit 1 of the debug control register.
An external debugger forces the processor into debug
state by asserting this signal.
Input to the EmbeddedICE-RT logic allows
breakpoints/watchpoints to be dependent on external
conditions.
Indicates that the instruction in the Execute stage of
the processor pipeline has been executed.
Indicates that the corresponding EmbeddedICE-RT
watchpoint register has matched the conditions
currently present on the address, data and control
buses. This signal is independent of the state of the
watchpoint enable control bit.
Signal Descriptions
A-9
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