Data Read From I-Sram; Data Read Followed By Instruction Fetch - ARM ARM966E-S Technical Reference Manual

ARM DDI 0186A
RDATA[31:0]
The stall cycle is only incurred for the first read of a read instruction. If an
performed, there is a stall cycle inserted only for the first read of the
s will incur a stall cycle at the start of each
LDR

Data read followed by instruction fetch

Data reads to the I-SRAM are pipelined. An instruction fetch in the cycle after a data
read request coincides with the stalled data read and so the instruction fetch is stalled
for 1 cycle. This is shown in on page C-6.
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CLK
DnMREQ
DnRW
Addr A (read)
DA[31:0]
SRAM Addr
SYSCLKEN
LDR
SRAM Stall Cycles
SRAM SRAM
stall cycle read cycle
Addr A
Read data
Figure C-4 Data read from I-SRAM
. Back-to- back
LDM
.
LDM is
C-5