Figure 6-7 Single Ldm, No Instruction Access; Stm Followed By Instruction Fetch - ARM ARM966E-S Technical Reference Manual

Bus Interface Unit
CLK
HBUSREQ
HGRANT
HTRANS
HADDR
HWRITE
HWDATA
HREADY
6-12
NONSEQ
DA-1
Note
HBUSREQ is driven LOW after two IDLE cycles which are inserted after a
immediately followed by an external instruction access. An
by any other AHB data access, also results in two IDLE cycles being inserted between
the two accesses.

STM followed by instruction fetch

Figure 6-8 on page 6-13 shows an example of an
immediately followed by an instruction fetch. The instruction read begins with a
NONSEQ/IDLE sequence after the final sequential data access. In this example,
subsequent instruction fetches are sequential.
Copyright © 2000 ARM Limited. All rights reserved.
SEQ SEQ
DA-2
DD-1 DD-2

Figure 6-7 Single LDM, no instruction access

IDLE
DA-3
DD-3
, immediately followed
LDM
transferring three words,
STM
ARM DDI 0186A
that is
LDM