Clock Interface Signals; Table A-1 Clock Interface Signals - ARM ARM966E-S Technical Reference Manual

A.2

Clock interface signals

ARM DDI 0186A
Table A-1 describes the ARM966E-S clock interface signals.
Name Direction
CLK Input
System clock
HCLKEN Input
DBGTCKEN Input
HRESETn Input
Not reset
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Table A-1 Clock interface signals

Description
This clock times all operations in the ARM966E-S
design. All outputs change from the rising edge and
all inputs are sampled on the rising edge. The clock
might be stretched in either phase.
Through the use of the HCLKEN signal, this clock
also times AHB operations.
Through the use of the DBGTCKEN signal, this
clock also times debug operations.
Synchronous enable for AHB transfers. When HIGH
indicates that the next rising edge of CLK is also a
rising edge of HCLK in the AHB system in which
the ARM966E-S is embedded. HCLK must be tied
HIGH in systems where CLK and HCLK are
intended to be the same frequency.
Synchronous enable for debug logic accessed by the
JTAG interface. When HIGH on the rising edge of
CLK the debug logic is able to advance.
Asynchronously asserted LOW input used to
initialize the ARM966E-S system state.
Synchronously de-asserted.
Signal Descriptions
A-3