ARM ARM966E-S Technical Reference Manual page 78

Bus Interface Unit
6.4.1 CLK to HCLK skew
6-18
If the slave being accessed at the HCLK rate has a multi-cycle response, the HREADY
input to the ARM966E-S is driven LOW until the data is ready to be returned. The BIU
must therefore perform a logical AND on the HREADY response with HCLKEN to
detect that the AHB transfer has completed. When this is the case, the ARM9E-S core
can then be enabled by reasserting SYSCLKEN.
Note
When an AHB access is required, the core must be stalled until the next HCLKEN
pulse is received, before it can start the access, and then until the access has completed.
This stall before the start of the access is a synchronization penalty and the worst case
can be expressed in CLK cycles as the CLK to CLK ratio minus one.
The ARM966E-S drives out the AHB address on the rising edge of CLK when the
HCLKEN input is true. The AHB outputs have output hold and delay values relative to
CLK. However, these outputs are used in the AHB system where HCLK is used to time
the transfers. Similarly, inputs to the ARM966E-S are timed relative to HCLK but are
sampled within the ARM966E-S with CLK. This leads to hold time issues from CLK
to HCLK on outputs and from HCLK to CLK on inputs. In order to minimize this
effect the skew between HCLK and CLK must be minimized.
Clock tree insertion at top level
Considering the skew issue in more detail, the ARM966E-S has a clock tree inserted to
allow an evenly distributed clock to be driven to all the registers in the design. The
registers that drive out AHB outputs and sample AHB inputs are timed off CLK' at the
bottom of the inserted clock tree and subject to the clock tree insertion delay. To
maximize performance, when the ARM966E-S is embedded in an AHB system, the
clock generation logic to produce HCLK must be constrained so that it matches the
insertion delay of the clock tree within the ARM966E-S. This can easily be achieved by
a clock tree insertion tool if the clock tree is inserted for the ARM966E-S and the
embedded system at the same time (top level insertion).
Figure 6-14 on page 6-19 shows an example of an AHB slave connected to the
ARM966E-S.
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