Chapter 4 Timing Requirements; Ahb Interface; Table 4-1 Ahb Interface Timing Requirements; Figure 4-1 Ahb Interface Signals - ARM ETB11 Technical Reference Manual

Timing Requirements
4.1

AHB interface

HCLK
HRDATAMEM
HRESP,
HREADYMEM
HADDR,
HWDATA
HWRITE,
HTRANS,
HSIZE,
HREADY,
HSELREG,
HSELMEM
HRESETn
4-2
The timings for the AHB interface signals are shown in Figure 4-1.
T
ovhdata
T
ovhcon
The timing requirements for the AHB interface are listed in Table 4-1. All figures are
expressed as percentages of the HCLK period at maximum operating frequency.
Note
A 0% figure in Table 4-1 indicates the hold time to clock edge plus the maximum clock
skew for internal clock buffering.
Parameter
T
ovhdata
T
ohhdata
T
ovhcon
T
ohhcon
T
ishdata
Copyright © 2002, 2003 ARM Limited. All rights reserved.
T
ohhdata
T
ohhcon
T T
ishdata ihhdata
T T
ishcon ihhcon
T T
ishresetn ihhresetn

Table 4-1 AHB interface timing requirements

Description
Rising HCLK to HRDATAMEM valid
HRDATAMEM hold time from HCLK rising
Rising HCLK to AHB control outputs valid
AHB control outputs hold time from HCLK rising
AHB data inputs setup to rising HCLK

Figure 4-1 AHB interface signals

Max
40%
-
40%
-
-
ARM DDI 0275D
Min
-
>0%
-
>0%
30%