Fig. 2.11 Timer Operation - Fujitsu F2MC-8L Family series Hardware Manual

Peripherals
Count-clock pulse
TPE
P41/PWM
TIR bit setting
Value of COMR
HARDWARE CONFIGURATION
(4) Description of operation
(a) Timer function
Setting the P/TX bit of the CNTR to 0 gives the timer-operation mode. When
the TPE bit of the CNTR is set to 1, the counter starts incrementing from
. When the value of the counter agrees with that of the COMR, the
00
H
counter is cleared on the next count clock pulse and incrementing restarts.
Therefore, the TIR bits are set and the output pin is reversed (but, when
the TPE bit is 0, the output pin is fixed at Low level) in cycles of the count
clock pulses when 00 is written at the COMR, or in cycles 256 times longer
H
than those of the count clock pulses when FF
If the value of the COMR is rewritten in the timer-operation mode, it becomes
effective from the next cycle (when the value of the counter is 00
of the COMR is transferred to the comparator latch).
00 00 00
00

Fig. 2.11 Timer Operation

If the TIE bit of the CNTR is set to 1, an interrupt occurs when the values
of the counter and COMR match. During interrupt processing, the TIR bit
is used as the interrupt flag. The TIR bit is set irrespective of the value of
the TIE bit. However, if the values of the counter and COMR match, the
TIR bit is set to 1 even after an interrupt is disabled.
Writing 0 at the TIR bit permits clearing of the interrupt source or the TIR
bit. When the Read Modify Write instruction is read, the TIR bit is set so
that 1 can always be read to prevent erroneous clearing.
By using P0 and P1 bit in CNTR, 1 out of 4 clock sources can be selected
for the counter.
2– 28
is written.
H
00 00 01
FF
, the value
H
FF 00