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CHAPTER 7 MODE SETTING
7.3 Mode Data
7.3
Mode Data
The mode data is located on the memory of the FFFFDF
operation after the reset sequence. The mode data is automatically taken into the CPU
by a mode fetch.
■ Mode Data
While executing the reset sequence, the mode data in the FFFFDF
register in the CPU core. CPU sets the memory access mode by this mode data. The values of the mode
register can be changed only in the reset sequence. The setting of the mode data is enabled after the reset
sequence.
Figure 7.3-1 shows the configuration of the mode data.
■ Set Bit of Bus Mode (M1, M0)
The M1 and M0 bits specify the operation mode after the reset sequence.
Table 7.3-1 shows the content of the M1, M0 bit setting.
Table 7.3-1 Content of M1 and M0 Bit Setting
M1
0
0
1
1
Note:
MB90335 series can be used on the single chip mode only. Please set M1, M0 = 00
160
Figure 7.3-1 Bit Configuration of Mode Data
bit
7
6
M1 M0
Mode data
Bus setting bit
M0
0
Single-chip mode
1
(Setting prohibited)
0
(Setting prohibited)
1
(Setting prohibited)
FUJITSU MICROELECTRONICS LIMITED
address and specifies the
H
5
4
3
2
0
0
0
0
Function extended bit
(Reserved area)
Function
MB90335 Series
address is captured into the mode
H
1
0
0
0
.
B
CM44-10137-6E
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