I2C Bus; Table 2. Hdmi Connector Pinout - ST STM32F100 Series Application Note

AN3127
Table 2.
Pin number
1
2
3
4
5
6
7
8
9
10
2.1.1

I2C bus

The display data channel (DDC) I/Os and wires (SDA, SCL, DDC/CEC Ground), should
meet the requirements specified in the I²C bus specification, version 2.1 (Section 15 for
"Standard-Mode" devices).
Discussions about high-capacitance environments found in the I²C Specification section
(17.2 "Switched pull-up circuit for Fast-mode I²C-bus devices") also apply to the HDMI
environment.
This section covers the electrical specifications for the I²C (defined by the CTS and by the
I²C bus specification). Timing specifications are not dealt with here. The HDMI standard
specifies that the maximum clock rate is 100 kHz.
The I²C bus is a standard two-wire (SCL for clock and SDA for data) serial databus protocol.
The electrical specifications for I²C bus device I/Os are power-supply-dependent. An I²C bus
device with fixed input levels of 1.5 V and 3 V can have its own supply voltage. A pull-up
resistor has to be connected to a 5 V ±10% supply.
When devices with fixed input levels are mixed with devices with input levels dependent on
V , the latter have to be connected to a common 5 V ±10% supply line with pull-up
CC
resistors connected to their SDA and SCL pins.
The ST reference board implemented in this application note has 3.3 V-tolerant I/Os and a
HDMI-compatible I²C bus dependent on a +5 V V
recommended to use the setup shown in
HDMI connector pinout
Signal name
TMDS Data 2+
TMDS Data 2 Shield
TMDS Data 2-
TMDS Data 1+
TMDS Data 1 Shield
TMDS Data 1-
TMDS Data 0+
TMDS Data 0 Shield
TMDS Data 0-
TMDS Clock+
Doc ID 16896 Rev 2
Pin number
11
12
13
14
15
16
17
18
19
-
supply. For the implementation, it is
CC
Figure 11, with the HDMI2C1-5DIJ chip.
Hardware environment
Signal name
TMDS Clock Shield
TMDS Clock-
CEC
No Connect
DDC Clock
DDC Data
Ground
+5 V power
Hot Plug Detect
-
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