User Manuals: IBM PPC750FX CPU

Manuals and User Guides for IBM PPC750FX CPU. We have 1 IBM PPC750FX CPU manual available for free PDF download: User Manual

IBM PPC750FX User Manual

IBM PPC750FX User Manual (116 pages)

Brand: IBM | Category: Motherboard | Size: 1 MB

Table of Contents

Evaluation Board
1
Table of Contents
3
Tables

7
Figures

9
About this Book

11
1 Overview

13
2 Board Design

19
- Processor
  19
- Figure 2-1. PPC750FX Board Architecture
  19
- Board Clocking
  20
- Figure 2-2. Clock Distribution on the PPC750FX Board
  20
- Internal Processor Clocking
  21
- System Controller
  21
- SDRAM Interface
  21
- PCI Bus
  21
- Ethernet
  21
- Table 2-1. Ethernet Ports
  21
- Flash Memory
  22
- Figure 2-3. Board Ethernet Architecture
  22
- Table 2-2. Switch Settings
  23
- Table 2-3. Flash Configurations
  23
- Nvram
  24
- Sram
  24
- Serial Ports
  24
- Figure 2-4. Board Serial Port Architecture
  24
- Logic Analyzer Connections
  25
- Power Supply
  25
  - PCI Voltages
    25
  - System Controller Voltages
    25
  - PPC750FX Voltages
    25
  - SDRAM Voltages
    26
- Form Factor
  26
3 Memory Map

27
- CPLD Register Definitions
  27
- Table 3-1. Board Address Space Usage
  27
- Table 3-2. Register0
  27
- Table 3-3. Register1
  28
- Table 3-4. Register2
  28
- Table 3-5. Register3
  29
- Table 3-6. Register4
  29
4 Programming the System Controller

31
- Ddr Sdram
  31
  - SDRAM Controller Initialization
    31
- Device Controller Bank Register Settings
  31
5 Reset and Interrupts

37
- Resets
  37
- Interrupts
  37
- Figure 5-1. Interrupt Architecture
  37
- Table 5-1. External Interrupts
  38
6 Switches

39
7 Fuses, Batteries, Regulators, and Fans

45
8 Displays

47
- Table 8-1. Displays
  47
- Figure 8-1. Display Location Diagram
  47
9 Jumpers

49
10 Connectors

53
11 CPLD Programming

73
- Programming-Registers and Control Functions
  73
  - I/O Pin List
    73
  - Table 11-1. Section Contents
    73
  - Table 11-2. CPLD I/O Pin List
    73
  - CPLD Logic
    76
    
    Table 11-3. CPLD Logic Descriptions
    76
    
    Top Level Block Diagram 1
    77
    
    Top Level Block Diagram 2
    78
    
    Framcs Logic
    79
    
    Decode_Block Program
    80
    
    Registers2 Program
    84
    
    Reset_Block Program
    89
    
    Misc Logic
    93
- Timing-Registers and Control Functions
  94
  - Maximum Clock Frequency
    94
  - Clock-To-Output Time
    94
  - Table 11-4. Maximum Clock Frequency
    94
  - Table 11-5. Clock-To-Output Time
    94
  - Pin-To-Pin Signal Delay
    96
  - Table 11-6. Pin-To-Pin Signal Delay
    96
  - Setup and Hold Time
    100
  - Table 11-7. Setup and Hold Time
    100
12 Bills of Materials

101
Index

113
Revision Log

115

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