Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3321

FFTA Programming Model
plus time taken to compute the FFT/IFFT plus the time taken to dump the output data. CCES provides an FFTA
version of these functions/APIs and the APIs supporting this use case always operate in synchronous mode.
Figure 50-2: Single-Shot
Pipelined Small FFT
The piplined small FFT is used where an FFT/IFFT operation with a fixed number of points is performed continu-
ously on more than one set of input data. The FFTA architecture supports pipelining of the input and output data
which allows the FFTA to load one set of input data and dump another set of processed output data in parallel while
another set of data (fetched in the previous pipeline cycle) is being processed. This helps to suppress the input and
output DMA overheads while the FFTA compute engine is busy processing the data. This way, programs can take
maximum advantage of the FFT compute engine's performance.
To support such cases, the FFTA APIs provide a mechanism where the FFTA is configured one time to perform the
FFT/IFFT operation with a fixed number of points in a continuous pipelined manner. Next, the APIs related to the
data transfers (asynchronous) are called to send the input data to and collect the output data from the FFTA. After
all the data is processed, the FFTA can be closed. For more details on these APIs, refer to the CCES RTL manual.
The Pipelined Small FFT figure illustrates this use case. There is large startup latency (Input DMA time + Compute
time + Output DMA time) involved to fill the pipeline with three frames. After that, each frame can be processed in
a lesser steady state time (maximum of Input DMA time, Compute time, and Output DMA time).
Figure 50-3: Pipelined Small FFT
Pipelined Small Interleaved FFT and IFFT Operations
Pipelined small interleaved FFT and IFFT operations are useful when data is first converted to the frequency do-
main, processed in the frequency domain and converted back to the time domain. The Typical Data Flow
50–6
INPUT N
COMPUTE N
OUTPUT
cfft(N)/ifft(N)/rfft(N)
EXECUTION
TIME
INPUT N N + 1
COMPUTE N
OUTPUT
STARTUP LATENCY
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
N + 1
N + 1
N N + 1
cfft(N+1)/ifft(N+1)/rfft(N+1)
EXECUTION
TIME
N + 2 N + 3 N + 4
N + 1 N + 2 N + 3
N N + 2
N + 1
STEADY STEADY
STATE STATE
EXECUTION EXECUTION
TIME TIME