Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3324

5. The output sections generated in 4. are overlapped and added with the existing output delay line.
6. The left most 512 samples from the output delay line generated in 6. are extracted to generate 512 output
samples corresponding to the original 512 input samples.
7. The delay line is then shifted left by 512 samples which is used as an input for the next processing iteration.
ADSP-SC58x FFTA Register Descriptions
High-Speed FFT Compute Unit (FFTA) contains the following registers.
Table 50-5: ADSP-SC58x FFTA Register List
Name
FFTA_CTL
FFTA_INST[nn]
FFTA_LC[nn]
FFTA_PC
FFTA_SCALE
FFTA_STAT
FFTA_THREADOFFSET
FFTA_WCTL
FFTA_XFRLEFT[nn]
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description
Control Register
Instruction Memory Register
Loop Counter Value Register
Program Counter Register
FFT/IFFT Scale Factor Register
Status Register
Thread Count Offset Register
Wrapper Control Register
Load/Dump Transfer Left Register
ADSP-SC58x FFTA Register Descriptions
50–9