Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3402

Table 52-12: IIR_CTL1 Register Fields (Continued)
Bit No.
(Access)
11 CCINTR
(R/W)
10 SS
(R/W)
9 CAI
(R/W)
8 DMAEN
(R/W)
5:1 CH
(R/W)
0 EN
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Channel Complete Interrupt.
The IIR_CTL1.CCINTR bit configures the channel complete interrupt to generate
when all channels are done or after each channel is done.
Save Biquad State.
The IIR_CTL1.SS bit configures the accelerator to store the Dk register settings in-
to the internal memory. This can be used to save the biquad states before switching to
another high priority accelerator task.
Channel Auto Iterate.
The IIR_CTL1.CAI bit sets whether TDM processing stops (idle) once all channels
complete processing or moves to first channel and continues TDM processing in a
loop when all channels complete processing.
DMA Enable.
The IIR_CTL1.DMAEN bit enables DMA on the accelerator.
Number of Channels.
The IIR_CTL1.CH bit field configures the number of channels and is programma-
ble between 0-23 (channels = NCH + 1).
IIR Enable.
The IIR_CTL1.EN bit enables or disables the IIR accelerator.
ADSP-SC58x IIR Register Descriptions
Description/Enumeration
0 Interrupt is generated only when all channels are done
(default)
1 Interrupt is generated after each channels is done (de-
fault)
0 TDM processing stops (idle) once all channels complete
processing
1 Moves to first channel and continues TDM processing
in a loop when all channels complete processing
0 Disable
1 Enable
0 IIR disabled
1 IIR enabled
52–21