Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3316

50 FFT Accelerator (FFTA)
The Fast Fourier Transform Accelerator (FFTA) performs memory to memory FFT/IFFT operations without core
software intervention. Additionally, the FFTA architecture allows execution of complex, pipelined, memory to mem-
ory algorithms including ping-ponged, windowed frequency domain filtering and very large FFTs. The FFTA may
also be used in conjunction with minimal computation support from a core in applications such as the overlap-add
operations required for large frequency-domain-based convolutions.
FFTA Features
The following list describes the FFTA features.
• Supports both complex and real FFT and IFFT operations.
• Supports 64, 128, 256, 512, 1024, 2048 points in small FFT mode and 4096, 8192, 16384, 32768, 65536,
131072, 262144, 524288, 1048576, 2097152, 4194304 points in large FFT mode.
• Supports the IEEE-754/854 single-precision floating-point data format, round to even.
• Radix-4 butterfly efficiency at a radix-2 (integer power of two) point granularity.
• Automatic insertion of zeros for real FFTs.
• Supports automatic conjugating of the twiddle factors for IFFT.
• Supports automatic scaling of FFT and IFFT inputs.
• Hardware support for windowing and frequency domain filtering.
• Hardware support for magnitude squared FFT output.
• Hardware support for pipelined data flow.
• Dedicated high speed DMA engines for data load and dump with a data width 64-bit clocked by SYSCLK.
• Supports data and coefficient access from both on-chip (L1/L2) and off-chip memories (L3).
• Optional support for bypassing the compute engine to perform high speed memory-to-memory MDMA trans-
fers.
• Clock division options for power reductions. Supports 1:1, 1:2, 1:4 and 1:8 clock ratio modes.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
FFT Accelerator (FFTA)
50–1