Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3383

Functional Description
• a coefficient memory size of 1440 × 40 bits (12 biquads × 24 channels × 5 coefficients)
• a data memory size of 576 × 40 bits (12 biquads × 24 channels × 2 states)
• one MAC unit with an input data buffer to supply data to the MAC
Figure 52-1: IIR Accelerator Block Diagram
The IIR accelerator is implemented using Transposed Direct Form II biquad which has less coefficient sensitivity.
The Transposed Direct Form II Biquad figure shows the signal flow graph for the biquad structure.
Figure 52-2: Transposed Direct Form II Biquad
The accelerator has the following logical subblocks.
• A datapath unit with the following elements:
• 32/40-bit coefficient memory (Ak, Bk) for storing biquad coefficients
• 32/40-bit input data (Xk) and state (Dk)
• One 40/32-bit floating-point multiplier and adder (MAC) unit
• An input data buffer to efficiently supply data to MAC
• One 40-bit result register to hold result of biquad
52–2
IIR CONTROL
IIR CONTROLLER
REGISTERS
BIQUAD
BIQUAD
CHANNEL 0
C
BIQUAD 0
O
Ak, Bk
E
F
F
CHANNEL 0
I
BIQUAD M
COEFF
C
Ak, Bk ACCESS
I
CONTROL
E
.
N
.
T
.
S
CHANNEL 0
BIQUAD 11
Ak, Bk
a
k0
x
k
X
a
k1
X
a
k2
X
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SCB BUS
DMA
CONTROLLER
RESULT
REGISTER
BIQUAD
DATA
BIQUAD
AND
COMPUTE
STATE
UNIT
ACCESS
(1 MAC)
CONTROL
y
+
k
d
k2
-1
Z
b
k1
+
X
d
k1
-1
Z
b
k2
+
X
I
BIQUAD
N
P
CHANNEL 0
U
BIQUAD 0
T
Xk, Dk
D
CHANNEL 0 A
BIQUAD M T
Xk, Dk A
.
&
.
.
S
T
A
CHANNEL 0
T
BIQUAD 11
E
Xk, Dk