Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3298

HAE Programming Concepts
is equal to 1, the HAE monitors the fundamental components multiple times. The maximum index allowed in the
registers is 63.
HAE_H[nn]_INDX
As a reference, the Harmonic Engine Outputs and Registers where Values are Stored table presents the harmonic
engine outputs and registers that store the outputs.
Table 49-6: Harmonic Engine Outputs and Registers where Values are Stored
Quantity
RMS of the Fundamental Component V
RMS of a Harmonic Component
Active Power of the Fundamental
Component
Active Power of a Harmonic Compo-
nent
Reactive Power of the Fundamental
Component
Reactive Power of a Harmonic Com-
ponent
Apparent Power of the Fundamental
Component
Apparent Power of a Harmonic Com-
ponent
Power Factor of the Fundamental
Component
Power Factor of a Harmonic Compo-
nent
Harmonic Distortion of a Harmonic
Component
Configuring Harmonic Calculations Update Rate
The harmonic engine functions at an 8 kHz rate. From the moment the
harmonic indexes are set in the
to settle within the specification parameters.
The HAE module uses the HAE_CFG2.UPDATE bits to manage the update rate of the output registers for the
harmonic engine. It manages the update rate independent of the calculations rate of 8 kHz for the engine. The de-
fault value of 000 means that the registers are updated every 125 uSec (8 kHz rate). Other update periods are: 250
uSec (001), 1 mSec (010), 16 mSec (011), 128 mSec (100), 512 mSec (101), 1.024 mSec (110). If the
HAE_CFG2.UPDATE bits are 111, the harmonic calculations are disabled.
The HAE module provides two ways to manage the harmonic computations. It enables the first approach when bit
HAE_CFG2.MODE is cleared to its default value of 0. The state sets status bit HAE_STAT.TXIRQ to 1 after a
49–16
Definition
, I
1 1
V , I , n = 2, 3,..., 12
n n
− γ
P = V I cos(φ )
1 1 1 1 1
P = V I cos(φ – γ ), n = 2, 3,..., 12
n n n n n
− γ
Q = V I sin(φ )
1 1 1 1 1
− γ
Q = V I sin(φ ), n = 2, 3,..., 12
n n n 1 1
S = V I
1 1 1
S = V I , n = 2, 3, ..., 12
n n n
P
( )
= ×
1
pf sgn Q
1
1
S
1
P
( )
= sgn ×
n
pf Q , n = 2, 3,..., 12
n n
S
n
V I
= =
n n
HD , HD , n = 2, 3,..., 12
V I
V I
n n
1 1
index registers, the HAE calculations take typically 750 mSec
HAE_H[nn]_INDX
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
HAE Registers
F_VRMS, F_IRMS
Hnn_VRMS, Hnn_XIRMS
F_ACT
Fnn_ACT
F_REACT
Hnn_REACT
F_APP
Hnn_APP
F_PF
Hnn_PF
Hnn_VHDN, Hnn_IHDN
HAE_CFG2 register is initialized, and the