Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3119

Packet Engine DMA Configuration Register
The
PKTE_DMA_CFG
tions IDLE cycles between two bus transfers.
MXBRSTSZ (R/W)
Max Burst Size
Figure 44-17: PKTE_DMA_CFG Register Diagram
Table 44-43: PKTE_DMA_CFG Register Fields
Bit No.
(Access)
20 IDLE
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register configures the maximum burst transfer size, enables incremental transfers, and inser-
15 14 13 12 11
0 0 0 0 0
31 30 29 28 27
0 0 0 0 0
IDLE (R)
Idle Enable
INCR (R)
Increment Enable
Bit Name
Idle Enable.
The PKTE_DMA_CFG.IDLE bit allows the peripheral bus master to insert one addi-
tional IDLE transfer between two successive peripheral bus master burst operations.
This provides the arbiter one additional cycle to hand over the grant to another periph-
eral bus master.
10 9 8 7 6 5 4 3
0 0 0 0 0 0 0 0
26 25 24 23 22 21 20 19
0 0 0 0 0 0 1 1
Description/Enumeration
0 The peripheral bus master inserts no IDLE cycle be-
tween two successive burst operations
1 The peripheral bus master inserts one additional IDLE
transfer between two successive burst operations
ADSP-SC58x PKTE Register Descriptions
2 1 0
1 1 0
18 17 16
0 0 0
MSTRBIGEND (R)
Master Big Endian
44–71