Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3406

IIR Debug Read Data High Register
The
IIR_DBG_RDDAT_HI
bits.
Figure 52-15: IIR_DBG_RDDAT_HI Register Diagram
Table 52-16: IIR_DBG_RDDAT_HI Register Fields
Bit No.
(Access)
7:0 VALUE
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register is part of the 40-bit wide debug mode read data register and holds the upper 8
15 14 13 12
0 0 0
VALUE (R)
Debug Read Data Highest 8 bits
31 30 29 28
0 0 0
Bit Name
Debug Read Data Highest 8 bits.
The IIR_DBG_RDDAT_HI.VALUE bit field holds the upper 8-bit read data.
11 10 9 8 7 6 5
0 0 0 0 0 0 0 0
27 26 25 24 23 22 21 20
0 0 0 0 0 0 0 0
Description/Enumeration
ADSP-SC58x IIR Register Descriptions
4 3 2 1 0
0 0 0 0 0
19 18 17 16
0 0 0 0 0
52–25