Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3387

Operating Modes
Operating Modes
The accelerator operates in
Window Processing Mode
Sample-based processing mode is selected by configuring window size to 1. In this mode, one sample from a particu-
lar channel is processed through all the biquads of that channel and the final output sample is calculated.
In window-based mode, multiple output samples (up to 1024) equal to the window size of that channel are calculat-
ed. After these calculations are complete, the accelerator begins processing the next channel. A configurable window
size parameter is provided to specify the length of the window.
40-Bit Floating-Point Mode
In 40-bit floating-point mode, the input data/coefficient is treated as a 40-bit floating-point number. 40-bit float-
ing-point MAC operations generate 40-bit results. This mode can be selected by setting the
IIR_CTL1.FORTYBIT bit.
Since the DMA bus width is 32 bits, in 40-bit mode the IIR accelerator performs two packed 32-bit accesses to the
memory to:
• fetch one 40-bit input or coefficient data, or
• to store one 40-bit output word
The first 32-bit word provides the lower 32 bits and the 8 LSBs of the second 32-bit word provides rest of the upper
8 bits of the complete 40-bit word. The 32-Bit to 40-Bit Packing figure shows the 32–40 bit packing used by accel-
erator.
NOTE: Overheads could be required to pack the input 40-bit data into the format acceptable by the IIR accelera-
tor and for unpacking the output of accelerator to the format acceptable by the rest of the application.
Figure 52-4: 32-Bit to 40-Bit Packing
Save Biquad State Mode
The IIR_CTL1.SS bit completely stores the current biquad states in local memory (writes all the DK1 and DK2
states back into the system memory states). This functionality is useful in applications that require fast switching to
another high-priority accelerator task—a required IIR to FIR processing transition for example. After resuming,
these states can be reloaded and IIR processing can be continued. Note that the DMA status is automatically stored
after each iteration.
52–6
Window Processing Mode,
X
DATA 1 [39—0]
X+1
X+2
DATA 2 [39—0]
X+3
3 COLUMN INTERNAL
MEMORY (40-BIT)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
40-Bit Floating-Point Mode
DATA 1 [31—0]
DATA 1 [39—31]
DATA 2 [31—0]
DATA 2 [39—31]
IIR ACCELERA TOR
(40-BIT) MEMORY
DMA BUS (32-BIT)
and Save Biquad State
DATA 1 [39—0]
DATA 2 [39—0]
Mode.