Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3125

Packet Engine Halt Status Register
The
PKTE_HLT_STAT
debugging purposes while processing in autonomous ring mode or target command mode. When the packet engine
is halted, the host can read all internal registers for examination without side effects. The host should not write to
any registers.
WRRD (R)
Halt On Write Result Descriptor
WRSA (R)
Halt On Write SA
WRDAT (R)
Halt On Write Data
DATSTATE (R)
Data State
RDSASTATE (R)
Read SA State
Figure 44-20: PKTE_HLT_STAT Register Diagram
Table 44-46: PKTE_HLT_STAT Register Fields
Bit No.
(Access)
26:24 DATSTATE
(R/NW)
23:20 RDSASTATE
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register reflects the status of the packet engine in halt mode. This register can be used for
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
Bit Name
Data State.
The PKTE_HLT_STAT.DATSTATE bit field indicates the state of the packet engine
read data FSM.
Read SA State.
The PKTE_HLT_STAT.RDSASTATE bit field indicates the state of the packet en-
gine read SA FSM.
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
Description/Enumeration
0 DATA_IDLE, no operation
1 DATA_READ
2 DATA_WRITE
3 DATA_WAIT
5 DATA_PAD_READ
6 DATA_BYP_READ
7 RESERVED
ADSP-SC58x PKTE Register Descriptions
EN (R)
Halt Mode Enabled Status
RDCD (R)
Halt On Read Command Descriptor
RDSA (R)
Halt On Read SA
MNSTATE (R)
Main State
44–77