Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3371

ADSP-SC58x FIR Register Descriptions
FIR Input Data Base Register
The register contains the input word base address with the lower two bits removed.
FIR_INBASE
VALUE[29:16] (R/W)
Word Address with Lower 2 Bits Removed
Figure 51-19: FIR_INBASE Register Diagram
Table 51-20: FIR_INBASE Register Fields
Bit No.
(Access)
29:0 VALUE
(R/W)
51–36
15
0
VALUE[15:0] (R/W)
Word Address with Lower 2 Bits Removed
31
0
Bit Name
Word Address with Lower 2 Bits Removed.
The FIR_INBASE.VALUE bit field contains the the word address with the lower 2
bits removed.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
14 13 12 11 10 9 8 7
0 0 0 0 0 0 0 0
30 29 28 27 26 25 24 23
0 0 0 0 0 0 0 0
Description/Enumeration
6 5 4 3 2 1 0
0 0 0 0 0 0 0
22 21 20 19 18 17 16
0 0 0 0 0 0 0