Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3210

PKA Most-Significant-Word of Divide Remainder
The register indicates the (32-bit word) address in the PKA RAM where the most significant non-
PKA_DIVMSW
zero 32-bit word of the Remainder result for the basic Divide and Modulo operations is stored. Bits [4:0] are loaded
with the bit number of the most significant non-zero bit in the most significant non-zero word when MS one con-
trol bit is set. For Divide, Modulo and MS one reporting, this register is updated when the PKA_FUNC.RUN bit is
reset at the end of the operation.
For the complex sequencer controlled operations, updating bits [4:0] of this register with the actual result's most
significant bit location is done near the end of the operation. Note that the result is only meaningful if no errors
were detected and that for ECC operations, the
the result point only.
15
ZERO (R)
Remainder Result Vector is Zeros
31
Figure 45-8: PKA_DIVMSW Register Diagram
Table 45-30: PKA_DIVMSW Register Fields
Bit No.
(Access)
15 ZERO
(R/NW)
10:0 ADDR
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
14 13 12 11 10 9 8
1 0 0 0 0 0 0 0
30 29 28 27 26 25 24 23
0 0 0 0 0 0 0 0
Bit Name
Remainder Result Vector is Zeros.
The PKA_DIVMSW.ZERO bit shows the remainder result vector is all zeros, ignore
the address returned in bits [10:0].
Address of Most-significant Nonzero Word.
The PKA_DIVMSW.ADDR bit shows the address of the most significant non-zero 32-
bit word of the remainder result vector in PKA RAM.
PKA_DIVMSW register provides information for the x-coordinate of
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
Description/Enumeration
ADSP-SC58x PKA Register Descriptions
ADDR (R)
Address of Most-significant Nonzero
Word
45–27