Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3304

ADSP-SC58x HAE Register Descriptions
Configuration 3 Register
The register configures HAE data transfer operations by selecting the fundamental and potential of
HAE_CFG3
twelve additional harmonic channels. The selected harmonics have their data (results) transferred to memory using
DMA. First, the fundamental; followed by the selected channel n, in the order from the lowest to the highest num-
bered channel. Each selected channel has its eight result words transferred.
Figure 49-11: HAE_CFG3 Register Diagram
Table 49-11: HAE_CFG3 Register Fields
Bit No.
(Access)
12:0 CHANEN
(R/W)
49–22
15 14 13
0 0 0
CHANEN (R/W)
Channel n Enable
31 30 29
0 0 0
Bit Name
Channel n Enable.
Each HAE_CFG3.CHANEN bit enables the fundamental and potential of twelve addi-
tional harmonic data channels. The following enumerations apply to each bit. Bit 0
denotes the fundamental channel. Bits 1-12 denote the harmonic channels 1-12, ac-
cordingly.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
12 11 10 9 8 7 6 5
0 0 0 0 0 0 0 0
28 27 26 25 24 23 22 21
0 0 0 0 0 0 0 0
Description/Enumeration
0 Disable channel n
8191 Enable channel n
4 3 2 1 0
0 0 0 0 0
20 19 18 17 16
0 0 0 0 0