Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3348

DMA Access
The FIR accelerator has two DMA channels (accelerator input and output) to connect to the system memory. The
DMA controller fetches the data and coefficients from memory and stores the result.
Accelerator TCB
The location of the DMA parameters for the next sequence comes from the chain pointer register that points to the
next set of DMA parameters stored in the internal memory of the processor. In chained DMA operations, the pro-
cessor automatically initializes and then begins another DMA transfer when the current DMA transfer is complete.
Each new set of parameters is stored in a user-initialized memory buffer or TCB for a chosen peripheral.
Chain Pointer DMA
The DMA controller supports circular buffer chain pointer DMA. One transfer control block (TCB) must be con-
figured for each channel. The TCB contains:
• A control register value to configure the filter parameters (such as filter tap length, window size, sample rate
conversion settings) for each channel
• DMA parameter register values for the input data (delay line)
• DMA parameter register values for coefficient load
• DMA parameter register values for output data
Intermediate results in multi-iteration mode are saved in the output buffer.
As shown in the Circular Buffer Addressing figure, the accelerator loads the TCB into its internal registers and uses
these values to fetch coefficients and data and to store results. After processing a window of data for any channel, the
accelerator writes back the appropriate values to the
memory. Then, data processing can begin from where it left off during the next time slot of that channel.
The write-back value for input buffer is:
•
FIR_INIDX + W for single rate filtering
•
FIR_INIDX + W × M for decimation (M = decimation ratio)
•
FIR_INIDX + W/L for interpolation (L = interpolation ratio)
• The write-back value for output buffer in floating point mode is:
• The write-back value for output buffer in fixed-point mode is:
The
NOTE: FIR_CTL2
channels with different control attributes.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register is part of the FIR TCB. This configuration allows programming individual FIR
FIR_INIDX and FIR_OUTIDX
FIR_OUTIDX
FIR_OUTIDX
Data Transfer
bit fields of the TCB in
+ W
+ 3 × W
51–13