Read Data Buffer (Rdb); Table 13.3.13A Time Required For Next Data Receive After Receive Buffer Full Interrupt Occurred - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

13.3.13 Read data buffer (RDB)

Read data buffer (RDB)
Address: 000081
H
Read/write
Initial value
This register (internally is a 8-byte FIFO buffer) stores received data in data field of the communication
frame. When eight byte data have been received, RDB becomes full and receive interrupt is generated.
Then data in RDB should be read out before the next coming byte of data is received as shown in
Table 13.3.13a . Otherwise, error will be occurred.
When error occurs in multiaddress reception, the communication ends. But when error occurs in normal
reception, the acknowledge bit will not returned to the transmitter. Then the transmitter will resend data
again until the maximum number of data transmitted is reached.
Even though RDB is not full, the receive interrupt will be generated when the number of data specified in
the telegraph field have been received, or the maximum number of data received in one communication
frame is reached. Once the receive interrupt has occurred, the data in RDB should be read out.
Writing '1' to WDBC in CMRL will clear all data in the buffer and return it as empty state.
This register can only be read when noit empty

Table 13.3.13a Time Required for next data receive after receive buffer full interrupt occurred

MB90580 Series
15 14 13
RD7 RD6 RD5
(R) (R) (R)
(X) (X) (X)
Maximum Time (us)
Mode 0
Mode 1
Mode 2
12 11 10
RD4 RD3 RD2
(R)
(R) (R)
(X)
(X) (X)
No. of Cycles
1580
400
290
13.3 Registers and Register Details
9 8
RD1 RD0
(R) (R)
(X) (X)
19000
4800
3400
Chapter 13: IE Bus
Bit Number
RDB
161