Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual page 87

BCM5718 Programmer's Guide
Bits Name
1 Link State Changed
2 Error
The Status Block format for these devices is as follows:
• Status Tag—Contains an unique eight-bit tag value in bits 7:0 when the Status Tagged Status mode bit of
the Miscellaneous Host Control register (see
page 282) is set to 1. This Status Tag can be returned to the Mailbox 0 register at location 31:24
(see"Interrupt Mailbox 0 Register (offset: 0x5800)" on page
Mailbox 0 register bits 23:0 are written as 0, the tag field of the Mailbox 0 register is compared with the tag
field of the last status block to be DMAed to host. If the tag returned is not equivalent to the tag of the last
status block DMAed to the host, the interrupt state is entered.
• Receive Producer Ring Consumer Index—Contains the controller's current Consumer Index value for the
Receive Producer Ring. This field indicates how many receive descriptors are in the receive producer ring
that the controller has consumed. For more information regarding this ring, see
page 77.
• Receive Return Rings 0–3 Producer Indices—Contain controller's current Producer Index value for the
each of the Receive Return Rings. When the controller receives a packet and writes that packet data into
host memory via DMA, it will increment the Producer Index for the corresponding Receive Return ring.
When a Producer Index is incremented, it is a signal to software that a newly arrived receive packet is
ready to be processed.
• Send Ring Consumer Index—Contains controller's current Consumer Index value for the Send Ring.
When the controller completes the read DMA of the host buffer associated with a send BD, the controller
will update the Send Ring Consumer Index. This provides the host software with an indication that the
controller has buffered this send data and, therefore, the host software may free the buffer that was just
consumed by the device.
Broadcom
®
January 29, 2016 • 5718-PG108-R
Table 19: Status Word Flags (Cont.)
Description
Indicates that link status has changed. This method of determining link change
status provides a small performance increase over doing a PIO read of the
Ethernet MAC Status register (see
page 311. See "Wake on LAN Mode/Low-Power" on page 212
of the PHY setup required when link state changes.
When this bit is asserted by the chip, the following conditions may have
occurred. Bit 2 of the status word is the OR of:
• All bits in Flow Attention register (0x3c48) (see
(offset: 0x3C48)" on page
• MAC_ATTN—Events from the MAC block (see
(offset: 0x404)" on page
• DMA_EVENT—Events from the following blocks:
– MSI (see "MSI Status Register (offset: 0x6004)" on page
– DMA_RD (see "LSO Read DMA Status Register (offset: 0x4804)" on
page 435.
– DMA_WR (see "Write DMA Status Register (offset: 0x4C04)" on
page 450.
• RXCP_ATTN—Events from RX RISC (see
0x5004)" on page 452.
"Miscellaneous Host Control Register (offset: 0x68)" on
"EMAC Status Register (offset: 0x404)" on
"Flow Attention Register
422.
"EMAC Status Register
311.
"RX RISC Status Register (offset:
460) by host driver. When the remaining
"Receive Producer Ring" on
Status Block
for a description
467.
Page 87