Eee Link Idle Status Register (Offset: 0X36C0); Eee Statistic Counter 1 Register (Offset: 0X36C4); Eee Statistic Counter 2 Register (Offset: 0X36C8); Eee Statistics Counter 3 Register (Offset: 0X36Cc) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

EEE Link Idle Status Register (offset: 0x36C0)

Name
Reserved
PCIE not in L0 State
Reserved
MDIO Idle
Debug UART Idle
APE TX Packet Buffer Empty 1
LAN TX Packet Buffer Empty

EEE Statistic Counter 1 Register (offset: 0x36C4)

Name
EEE Mode Entering Counter

EEE Statistic Counter 2 Register (offset: 0x36C8)

Name
Receive LPI Entering Counter 31:0

EEE Statistics Counter 3 Register (offset: 0x36CC)

Name
EEE Link Idle Entering Counter 31:0
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
31:25 RO 0x0
24 RO 0x0
23:4 RO 0x0
3 RO 0x0
2 RO 0x0
RO 0x0
0 RO 0x0
Default
Bits Access Value
31:0 RW 0x0
Default
Bits Access Value
RW 0x0
Default
Bits Access Value
RW 0x0
Central Power Management Unit (CPMU) Registers
Description
–
PCIE is in L0s, L1 or L2 state.
–
No on-going MDIO access.
Debug UART is idle.
Internal packet buffers in APE subsystem for TX
is empty.
Internal packet buffers in LAN core for TX is
empty.
Description
This counter counts the number of times CPMU
goes into EEE mode. The entire 32 bit register
can be cleared by writing 0xFFFFFFFF.
Description
This counter counts the number of times the
receive side goes into LPI. The entire 32 bit
register can be cleared by writing 0xFFFFFFFF.
Description
This counter counts the number of timers the
debounced version of EEE link idle is asserted.
The entire 32 bit register can be cleared by
writing 0xFFFFFFFF.
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