Flash Clock Policy Register (Offset: 0X366C) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide
Name
Incorrect checksum on LSO
packets Fix Disable
PCIE pcie_tmux_sel[1:0]
Reserved
PLLisUp signal drive
PCIE pcie_tmux_sel[3:2]
Reserved
Capability version for
completion timeout ECN for
PCIE 1.1
Reserved

Flash Clock Policy Register (offset: 0x366C)

For BCM5719/5720 only. This register is reset by POR Reset or CPMU Register Software Reset. The Force
Disable bit has higher priority than Override Enable. This register is shared by all 4 MAC ports. User must first
gain grant from the global MUTEX registers (0x36F0 & 0x36F4) before writing to this register.
Name
Flash Clock Speed
Force Flash Clock Disable
Flash Idle mode Enable
Force EAV Clock Disable
Reserved
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
20 RW 0x0
19:18 RW 0x0
17:13 DC 0
12 RW 0x0
11:10 RW 0x0
9 RW 0
8 RW 0x0
7:0 DC 0x0
Default
Bits Access Value
31 RW 0x0
30 RW 0x0
29 RW 0x0
28 RW 0x0
27:20 DC 0
Central Power Management Unit (CPMU) Registers
Description
Disable fix for incorrect checksum on LSO
packets.
1 = Disable
0 = Enable
–
–
When 0, force the PLLisUp signal to be 1.
When 1, let the hardware drive the PLLisUp
signal.
–
–
1 = Version 1; Fix Disable
0 = Version 2; Fix Enable
–
Description
Enable Flash clock override*.
Override Enable
1: Enable Flash clock override
0: Disable Flash clock override
Flash clock Disable*.
1: Disable Flash clock
0: Enable Flash clock
Flash Idle mode Enable
1: Enable Flash Idle mode
0: Disable Flash Idle mode
EAV clock Disable
1: Disable EAV clock
0: Enable EAV clock
–
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