BCM5718 Programmer's Guide
Name
FATAL_ERR_REPORT_EN
NFATAL_ERR_REPORT_EN 1
CORR_ERR_REPORT_EN
LINK_CAPABILITY – 0xb8
Name
PORT_NUMBER
Unused0
LINK_BW_NOTIFY
DL_ACTIVE_REP
SUR_DWN_ERR_REP
CLK_PWR_MGMT
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits
Access
Value
2
RW
0:pr
RW
0:pr
0
RW
0:pr
Default
Bits
Access
Value
31:24
RO
0
23:22
RO
0
21
RO
0
20
RO
0
19
RO
0
18
RO
0x1
Description
Fatal Error Reporting Enable.
Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
Non-Fatal Error Reporting Enable.
Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
Correctable Error Reporting Enable.
Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
Description
PCIE Port Number. These bits are programmable
through register. Path= i_cfg_func.i_cfg_private
–
Link Bandwidth Notification Capability: RC: A
value of 1b indicates support for the Link
Bandwidth Notification status and interrupt
mechanisms. This capability is required for all
Root Ports and Switch Downstream Ports
supporting Links wider than x1 and/or multiple
Link speeds. RC: Field is implemented. EP: Not
supported and hardwired to 0.
Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
Data Link Layer Link Active Reporting Capable:
RC: this bit must be hardwired to 1b if the
component supports the optional capability of
reporting the DL_Active state of the Data Link
Control and Management State Machine. RC:
Implemented (RW) for RC. Default to 0. EP: Not
supported and hardwired to 0.
Path= i_cfg_func.i_cfg_private
Surprise Down Error Reporting Capable: RC: this
bit must be set if the component supports the
optional capability of detecting and reporting a
Surprise Down error condition. RC: Not supported
and hardwired to 0. EP: Not supported and
hardwired to 0.
Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
Clock Power Management. These bits are
programmable through register. The feature itself
has to be enabled in version.v
Path= i_cfg_func.i_cfg_private
PCI Configuration Registers
Page 292
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