Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual page 444

BCM5718 Programmer's Guide
Name
Post-DMA Debug Enable
Address Overflow Error
Logging Enable
Reserved
PCI Request Burst Length
Reserved
Read DMA PCI-X Split
Transaction Timeout Expired
Attention Enable
Read DMA Local Memory
Write Longer Than DMA
Length Attention Enable
Read DMA PCI FIFO Overread
Attention Enable
Read DMA PCI FIFO Underrun
Attention Enable
Read DMA PCI FIFO Overrun
Attention Enable
Read DMA PCI Host Address
Overflow Error Attention
Enable
Read DMA PCI Parity Error
Attention Enable
Read DMA PCI Master Abort
Attention Enable
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
26 RO 0
25 RO 0
24:18 RO 0
17:16 RO 0
15:11 RO 0
10 RO 0
9 RO 0
8 RO 0
7 RO 0
6 RO 0
5 RO 0
4 RO 0
3 RO 0
Description
When this bit is set, the Send Data Completion
State Machine will be halted if the Post-DMA bit
of the Send BD is set
This bit when set, enables the address overflow
error to be generated when the DMA Read
Engine performs a DMA operation that crosses a
4G boundary. This error is reported in bit 3 of the
DMA Read Status Register. Subsequently, this
will generate an internal event to interrupt the
internal CPU and the DMA Read Engine will lock
up after detecting this error. So it is
recommended that this bit should not be set by
firmware or software.
1: Enable Address Overflow Error Logging
0: Disable Address Overflow Error Logging.
–
00 = 128 bytes
01 = 256 bytes
10 = 512 bytes
11 = 4096 bytes
Note: The actual size of the resulting PCIe
memory read transaction may be further limited
by the PCIe Maximum Read Request Size
(MRRS) field of the PCIe Device Status Control
Register (0xB4).
–
Enable read DMA PCI-X split transaction timeout
expired attention.
Enable Read DMA Local Memory Write Longer
Than DMA Length Attention.
Enable Read DMA PCI FIFO Overread Attention
(PCI read longer than DMA length.)
Enable Read DMA PCI FIFO Underrun Attention.
Enable Read DMA PCI FIFO Overrun Attention.
Enable Read DMA PCI Host Address Overflow
Error Attention. A host address overflow occurs
when a single DMA read begins at an address
below 4 GB and ends on an address above 4 GB.
This is a fatal error.
Enable Read DMA PCI Parity Error Attention.
Enable Read DMA PCI Master Abort Attention.
RDMA Registers
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