BCM5718 Programmer's Guide
Miscellaneous Control Register (offset: 0x36AC)
Name
Reserved
Speculative early L1 exit mode 25:24
Speculative early L1 exit delay 23:16
Reserved
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits
Access
Value
31:26
DC
0x0
RW
0x0
RW
0x0
15:0
DC
0x0
Central Power Management Unit (CPMU) Registers
Description
–
Mode control for speculative early L1 exit.
2'b00: Enable speculative early L1 exit when
Ethernet is linked to 1000 Mb/s only
2'b01: Enable speculative early L1 exit
regardless link speed
2'b10: Disabled speculative early L1 exit
2'b11: Reserved
Delay control for speculative early L1 exit
detection. The detection circuit uses the earliest
receive packet indicator after mac address
filtering circuit. Each increment increases the
delay by 10.240 µS.
0x0: no delay
0x1: 10.24 µs delay
0x2: 20.48 µs delay
..
..
0xFF: 2621.44 µs delay
The optimal value of this delay is a function of link
speed, packet size, L1 exit latency, L1 entrance
inactive timer value and the following simulation
data.
1000 MB/s 1518byte packet–advances l1aspm
exiting by 13.880 µs with no delay
1000 MB/s 64byte packet–advances l1aspm
exiting by 2.488 µs with no delay
100 MB/s 1518byte packet–advances l1aspm
exiting by 129.377 µs with no delay
100 MB/s 64byte packet–advances l1aspm
exiting by 13.217 µs with no delay
10 MB/s 1518byte packet–advances l1aspm
exiting by 1274.94 µs with no delay
10 MB/s 64byte packet–advances l1aspm
exiting by 113.98 µs with no delay
–
Page 406
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