Bd Read Dma Corruption Enable Control Register (Offset: 0X4A78); Non_Lso Read Dma Mode Register (Offset: 0X4B00) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

BD READ DMA Corruption Enable Control Register (offset: 0x4A78)

Name
Reserved
Enable hardware fix for wrong
TCP checksum
Reserved
Enable hardware fix for IP
Header checksum corruption
DMA Read Engine may be
unable to generate Memory
Read Request to PCIE Core
upon transitioning from L1 to
L0 with Clkreq Enable
Enable hardware fix for clock
switching problem
Enable hardware fix for PCIE
client lockup
Reserved
Reserved

Non_LSO Read DMA Mode Register (offset: 0x4B00)

Name
Reserved
Hardware IPv6 Post-DMA
Processing Enable
Hardware IPv4 Post-DMA
Processing Enable
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
31:8 RO 0
7 RO 0
6 RO 0
5 RO 0
4 RO 1
3 RO 1
2 RO 1
1 RO 0
0 RO 0
Default
Bits Access Value
31:29 RO 0
28 RO 0
27 RO 0
Description
–
0: Enable Fix
1: Disable Fix
–
This control bit is used to enable the fix for the IP
Header Checksum Corruption occurs when an
IPV4 payload contents match an IPV6 Header
Type.
1: Disable fix
0: enable fix
Set to 1 to enable fix for clock request gap
problem of Tx Read DMA lock-up issue.
Note that increasing the ASPM L1 entry time to a
value on the order of 1ms is recommended and
may prevent this issue from occurring. See
register 0x7d28.
Set to 1 to enable fix for clock switching problem
of Tx Read DMA lock-up issue.
Note that increasing the ASPM L1 entry time to a
value on the order of 1ms is recommended and
may prevent this issue from occurring. See
register 0x7d28.
Set to 1 to enable fix for Tx Read DMA lock-up
issue.
Note that increasing the ASPM L1 entry time to a
value on the order of 1ms is recommended and
may prevent this issue from occurring. See
register 0x7d28.
–
–
Description
–
Enables hardware processing of LSO IPv6
packets. This bit has no effect on Post-DMA
processing of IPv4 packets.
Enables hardware processing of LSO IPv4
packets. This bit has no effect on Post-DMA
processing of IPv6 packets.
RDMA Registers
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