Bd Fetch Limit Register (Offset 0X2D08); Receive Bd Completion Control Registers; Receive Bd Completion Mode Register (Offset: 0X3000); Receive Bd Completion Status Register (Offset: 0X3004) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

BD Fetch Limit Register (Offset 0x2D08)

This register is meaningful only in the IOV-Mode.
Name
Legacy
BD Fetch Limit

Receive BD Completion Control Registers

All registers reset are core reset unless specified.

Receive BD Completion Mode Register (offset: 0x3000)

Name
Reserved
Attention Enable
Enable
Reset

Receive BD Completion Status Register (offset: 0x3004)

Name
Reserved
Error
Reserved
Broadcom
®
January 29, 2016 • 5718-PG108-R

Table 106: BD Fetch Limit Register (Offset 0x2D08)

Default
Bits Access Value
31:5 RU 0x0
4:0 RW 0x1F
Default
Bits Access Value
31:3 RO 0
2 RW 0
1 RW 1
0 RW 0
Default
Bits Access Value
31:3 RO 0
2 RO 0
1:0 RO 0
Receive BD Completion Control Registers
Description
Unused
The number of BDs fetched by a single DMA
request shall be the lesser of the following:
• Space available in the respective BD cache.
• Standard or Jumbo Replenish Threshold.
• Number of BDs made available in the Host
memory based Ring.
• Programmed Value of this Field.
Description
–
When this bit is set to 1, an internal attention is
generated when an error occurs.
This bit controls whether the Receive BD
Completion state machine is active or not. When
set to 0, it completes the current operation and
cleanly halts. Until it is completely halted, it
remains one when read.
When this bit is set to 1, the Receive BD
Completion state machine is reset. This is a self-
clearing bit.
Description
–
Receive BD Completion Error Status.
–
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