Tx Time Stamp Msb Reg [Offset 0X05C4]; Rx Time Stamp Lsb Reg [Offset 0X06B0]; Rx Time Stamp Msb Reg [Offset 0X06B4]; Rx Ptp Sequence Id Reg [Offset 0X06B8] - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide
Name
TX Time Stamp [lower
half]

TX TIME STAMP MSB REG [Offset 0X05C4]

Name
TX Time Stamp [Upper
half]

RX TIME STAMP LSB REG [Offset 0X06B0]

Name
RX Time Stamp [lower
half]

RX TIME STAMP MSB REG [Offset 0x06B4]

This MSB and LSB pair captures the time-stamp (63-bits) of received PTP packets when qualified to do so. HW
overwrite of the Time Stamp value is controlled by an interlock policy – See
0X06C8]" on page 164. The MSB and LSB registers may be accessed in the order of LSB first and MSB second
– else the Valid / Interlock bit would not serve its purpose.
Name
RX Time Stamp Valid /
Interlock
RX Time Stamp [Upper
half]

RX PTP SEQUENCE ID REG [Offset 0X06B8]

Name
Reserved
Broadcom
®
January 29, 2016 • 5718-PG108-R
Bits Access Default Value Description
31:0 RO U
Bits Access Default Value Description
31:0 RO U
Bits Access Default Value Description
31:0 RO U
Bits Access Default Value Description
31 RO U
30:0 RO U
Bits Access Default Value Description
31:16 RO 0x0000
LSB of the TX Time Stamp – Reading this LSB
freezes the time stamp and is only unfrozen when
the corresponding MSB is read.
MSB of the TX Time Stamp – Reading this MSB
unfreezes the time stamp which was earlier frozen by
the corresponding LSB read.
LSB of the RX Time Stamp.
"RX PTP CONTROL REG [Offset
This bit is set by hardware in conjunction with posting
a new value in the Time Stamp MSB and LSB fields.
When this bit is 1 and SW executes a read to the RX
TIME STAMP MSB Register, hardware shall clear
this bit – the reset behavior of this bit is influenced by
RX PTP CONTROL Register's [RX TIME STAMP
INTERLOCK POLICY] field.
MSB of the RX Time Stamp.
Time Sync Registers
Page 163