Top Level Miscellaneous Control 1 Register (Offset: 0X367C) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

Top Level Miscellaneous Control 1 Register (offset: 0x367C)

For BCM5719/5720 only. This register is reset by POR Reset or CPMU Register Software Reset. This register
is shared by 4 MAC ports. User must first gain grant from the global MUTEX registers (0x36F0 & 0x36F4) before
writing to this register.
Name
Reserved
Low power IDDQ mode
NCSI Clock output disable
47147 fix disable
47173 fix disable
Debug UART Port Selection
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
31:6 RW 0
5 RW 0
4 RW 0
3 RW 0
2 RW 0
1 RW 0
Central Power Management Unit (CPMU) Registers
Description
–
1–Enable to put all ports in GPHY mode during
low power IDDQ to select GPHY mode to save
power.
0–SerDes mode in low power IDDQ mode by
default, draws more current
1–To enable the NCSI clock disable feature,
NCSI clock signal pin is driven low
0–NCSI clock output active (default)
47147 fix disable–PCIe MDIO reset fix disable.
1–Disable
0–Enable
47173 fix disable–CLKREQ_L tri-state fix
disable.
1–Disable
0–Enable
Select the Debug UART Port.
00: port0
01: port1
10: port2
11: port3
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