Vrq_Perfect_Match[4 - 23]_Low_Reg (Offsets: 0X5694, 0X569C, 0X56A4; Low Priority Mailboxes; Interrupt Mailbox 0 Register (Offset: 0X5800); Other Interrupt Mailbox Register (Offset: 0X5808-0X5818) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide
Table 117: VRQ_PERFECT_MATCH[4 – 23]_HIGH_REG (Offsets: 0x5690, 0x5698, 0x56A0 ... 0x5728)
Name
Reserved
MAC High Address
VRQ_PERFECT_MATCH[4 – 23]_LOW_REG (Offsets: 0x5694,
0x569C, 0x56A4 ... 0x572C)
There are total 24 Perfect (Destination Address) Match registers for VRQ Filtering in RX-MAC. These registers
hold the higher 2 octets of the matching address.
Table 118: VRQ_PERFECT_MATCH[4 – 23]_LOW_REG (Offsets: 0x5694, 0x569C, 0x56A4 ... 0x572C)
Name
MAC Low Address

Low Priority Mailboxes

This is a 512 byte region that contains 64 registers. These registers are called low-priority mailbox registers (or
low-priority mailboxes). When a value is stored in the least significant 32 bits of these registers, an event (known
as a Mailbox Event) is generated to the RX RISC. Host software should use the high-priority mailbox region from
0x200–0x3FF for host standard and the low-priority mailbox region from 0x5800–0x59FF for indirect register
access mode. The Mailbox registers starting at memory offset 0x200 for host standard and offset 0x5800 for
indirect mode.

Interrupt Mailbox 0 Register (offset: 0x5800)

This mailbox serves two functions. When the host writes it, the interrupt (IntA) is cleared. It is also used by the
Host Coalescing engine to determine if the host is in the interrupt handler. If it is non-zero this indicates the host
is in the interrupt handler. If it is zero this indicates the host is not in the interrupt handler. The Host Coalescing
engine uses this information to determine which set of coalescing parameters it should use.
Other Interrupt Mailbox Register (offset: 0x5808–0x5818)
This mailbox serves two functions. When the host writes it, the interrupt (IntA) is cleared. It is also used by the
Host Coalescing engine to determine if the host is in the interrupt handler. If it is non-zero this indicates the host
is in the interrupt handler. If it is zero this indicates the host is not in the interrupt handler. The Host Coalescing
engine uses this information to determine which set of coalescing parameters it should use.
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
31:29 RO 000
15:0 RW 0x0000
Default
Bits Access Value
31:0 RO 0x0000
Description
Reserved
Upper 2-bytes of MAC address
Description
Lower 4-bytes of MAC address
Low Priority Mailboxes
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